The system resets in Target Support Package TC2 3.1 (R2008b) because the Simulink scheduler timer ISR does not block and also clear pending same group interrupts (here the same scheduler ISR) until it finishes itself. So the higher priority EPWM TZ5 interrupt could preempt the base rate scheduler ISR before it ends, thus when this preemption ends, the pending base rate ISR could cause the scheduler to overrun and reset.
In Target Support Package TC2 3.2 (R2009a) this behavior does not occur since the GPIO 24 toggles forever when the EPWM4_TZINT interrupt is triggered.
For the R2008b release, use the following workaround to avoid the reset by manually editing the code as follows:
1. In the generated code MW_c28xx_csl.c, change the function TINT0_isr() to be the following:
interrupt void TINT0_isr(void)
{
volatile unsigned int PIEIER1_stack_save = PieCtrlRegs.PIEIER1.all;
PieCtrlRegs.PIEIER1.all &= ~64; //disable group1 lower/equal priority interrupts
asm(" RPT #5 || NOP"); //wait 5 cycles
IFR &= ~1; //eventually disable lower/equal priority pending interrupts
PieCtrlRegs.PIEACK.all = 1; //ACK to block other interrupts from the same group to fire
IER |= 1;
EINT; //global interrupt enable
rt_OneStep();
DINT; // disable global interrupts during context switch, CPU will enable global interrupts after exiting ISR
PieCtrlRegs.PIEIER1.all = PIEIER1_stack_save;//restore PIEIER register that was modified
}
2. In the xxx_main.c file, change rt_OneStep() to be as below:
Add following lines before the TZinterupt_EZDSP_step();
asm(" SETC INTM");
PieCtrlRegs.PIEIER1.all |= (1 << 6);
asm(" CLRC INTM");
Add the following lines after the TZinterupt_EZDSP_step();
asm(" SETC INTM");
PieCtrlRegs.PIEIER1.all &= ~(1 << 6); //disable group1 lower/equal priority interrupts
asm(" RPT #5 || NOP");
IFR &= 0xFFFE;
PieCtrlRegs.PIEACK.all = 0x1; //ACK to block other interrupts from the same group to fire
asm(" CLRC INTM");
Build and run the code in the Code Composer Studio.
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