MATLAB: How to add multiple AXI4 Master Interfaces to a reference design in HDL Coder

axiaxi4designHDL Codermastermultiplereference

How do I add multiple AXI4 Master Interfaces to a reference design in HDL Coder?

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To add multiple AXI4 Master interfaces, add multiple calls of 'addAXI4MasterInterface' to the reference design definition file (plugin_rd.m). For example:

hRD.addAXI4MasterInterface(...
'InterfaceID', 'AXI4 Master 1', ...
'ReadSupport', true, ...
'WriteSupport', true, ...
'MaxDataWidth', 128, ...
'AddrWidth', 32, ...
'InterfaceConnection', 'axi_interconnect_1/S01_AXI',...
'TargetAddressSegments', {{'mig_7series_0/memmap/memaddr',2*1024^3,2*1024^3}});
hRD.addAXI4MasterInterface(...
'InterfaceID', 'AXI4 Master 2', ...
'ReadSupport', true, ...
'WriteSupport', true, ...
'MaxDataWidth', 128, ...
'AddrWidth', 32, ...
'InterfaceConnection', 'axi_interconnect_1/S02_AXI',...
'TargetAddressSegments', {{'mig_7series_0/memmap/memaddr',2*1024^3,2*1024^3}});

To learn more about 'addAXI4MasterInterface', please refer the link below:

https://www.mathworks.com/help/releases/R2018b/hdlcoder/ref/hdlcoder.referencedesign.addaxi4masterinterface.html

Related Solutions

MATLAB: How to add multiple AXI4-Stream Interfaces to an IP Core generated by HDL Coder

As of MATLAB R2019a, HDL Coder only supports one Slave (input) AXI4-Stream interface, and one Master (output) AXI4-Stream interface per IP core. For many SDR and video applications, multiple input or output channels are needed.

At this time, a possible workaround is as follows:

1) In HDL Workflow Advisor Task 1.1, it is necessary to select a specific board for "Target platform" (e.g. "Zedboard"). If you select "Generic Xilinx Platform", it is not currently possible to support this workflow

2) Create and register a custom reference design for the selected board, following the workflow outlined here:

https://www.mathworks.com/help/releases/R2019a/hdlcoder/ug/register-a-custom-reference-design.html

To ease this process, you can refer to an existing reference design for the selected board. For example, on a Windows machine the AXI4-Stream reference design for the Zedboard could be found at:

 C:\ProgramData\MATLAB\SupportPackages\R2019a\toolbox\hdlcoder\supportpackages\zynq7000\+ZedBoard\+vivado_stream_2018_2

This will also require exporting a block design from Vivado. A full example of this workflow can be found here:

https://www.mathworks.com/help/releases/R2019a/hdlcoder/examples/define-and-register-custom-board-and-reference-design-for-zynq-workflow.html#d117e22885

3) In the custom reference design file (e.g. "plugin_rd.m"), call the "addAXI4StreamInterface" function multiple times to define multiple AXI4-Stream interfaces. Each one of these can be specified with a different Interface ID to distinguish them. For example, you might do the following in your custom reference design file:

% add first AXI4-Stream interface
hRD.addAXI4StreamInterface( ...
'MasterChannelNumber', 1, ...
'SlaveChannelNumber', 1, ...
'MasterChannelConnection', 'axi_dma_s2mm/S_AXIS_S2MM', ...
'SlaveChannelConnection', 'axi_dma_mm2s/M_AXIS_MM2S', ...
'MasterChannelDataWidth', 32, ...
'SlaveChannelDataWidth', 32, ...
'InterfaceID', 'AXI4-Stream_1');
% add second AXI4-Stream interface
hRD.addAXI4StreamInterface( ...
'MasterChannelNumber', 1, ...
'SlaveChannelNumber', 1, ...
'MasterChannelConnection', 'axi_dma_s2mm_2/S_AXIS_S2MM', ...
'SlaveChannelConnection', 'axi_dma_mm2s_2/M_AXIS_MM2S', ...
'MasterChannelDataWidth', 32, ...
'SlaveChannelDataWidth', 32, ...
'InterfaceID', 'AXI4-Stream_2');

4) Once this custom reference design is created, you can select it in HDL Workflow Advisor Task 1.2.

5) In HDL Workflow Advisor Task 1.3, you can now select from multiple AXI4-Stream interfaces. Note that due to the current limitations, it will be necessary to model and map the READY signals for all the AXI4-Stream interfaces.

MATLAB: Does synthesis fail for ZC706 or other high-cost boards when using free Vivado WebPACK edition

This error may be due to a Vivado licensing error. This can be confirmed by opening the Vivado Project File (.XPR) in Vivado IDE, which will reveal the following error on the "Messages" tab:

[Common 17-345] A valid license was not found for feature 'Synthesis' and/or device 'xc7z045'. Please run the Vivado License Manager for assistance in determining which features and devices are licensed for your system.

For example, the no-cost Vivado WebPACK edition only supports a limited set of commercial devices. See the following Xilinx documentation page for a list of all FPGA devices supported by WebPACK:

https://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html#architecture

While Vivado WebPACK supports the low-cost XC7Z020 device used on Zedboard and Xilinx ZC702, an additional license is required for the synthesis of the XC7Z045 Zynq device used on Xilinx ZC706.

Best Answer

Related Solutions

MATLAB: How to add multiple AXI4-Stream Interfaces to an IP Core generated by HDL Coder

MATLAB: Does synthesis fail for ZC706 or other high-cost boards when using free Vivado WebPACK edition

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