There is a subset of blocks that support HDL code generation in frame mode. This is equivalent to processing multiple samples per clock in the FPGA. You can see the subset of blocks included at the following link:
https://www.mathworks.com/help/dsp/ug/high-throughput-hdl-algorithms.html
Other than these blocks, there is no direct HDL code generation support for frame-based models since they execute multiple FPGA time steps in one Simulink time step. However, HDL code generation support is provided for the same blocks if the inputs are samples. You can thus convert the frame based communication to sample based communication in one of two ways:
a) At the border of your FPGA design, use the Frame Conversion block and convert the frames to samples.
b) Set your source to emit samples with frame size set to 1.
FPGA-in-the-loop does support frame inputs, so step (b) may work better. For HDL code generation, you can set frame size to 1, and when you move to FIL, you can set it to an appropriate frame size value.
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