MATLAB: HDL Workflow advisor not recognizing Target Platform: Speedgoat IO333, when Target workflow is set to Simulink Real-Time FPGA IO (running v R2016a)

io333kintex 7MATLABsimulinkspeedgoatspeedgoat performance

Setting up speedgoat performance to run HIL testing. Able to connect and run models with the Spartan 6 FPGA (IO331), however when I try to create basic models and run them on the Kintex 7 FPGA (IO333), IO333 is not recognized in the HDL Workflow Advisor, it only recognizes IO's up to IO331-6. Is there any other third party software needed for this other than Xilinx ISE? Or is there a separate way to connect and run models on the Kintex 7? – Couldn't find much mathworks/speedgoat documentation about running models on the Kintex 7.

Best Answer

To enable HDL Coder for Speedgoat FPGA-based I/O modules, you require a dedicated HDL Coder integration package. Also, while the IO331 (Spartan 6) requires Xilinx ISE 14.7, for the IO333 (Kintex 7) you need a specific Xilinx Vivado Suite; the version depends on your MATLAB release. See: www.speedgoat.com/help/page/configuration/refentry_host_software_installation#refsect1_xilinx_hdl_software

The HDL Coder package has to be purchased from Speedgoat, and will be available for download from the online portal (www.speedgoat.com/login).

Related Solutions

MATLAB: What is the difference between FPGA Turnkey and IP Core Generation

Hi Yashar,

Both IP Core Generation and FPGA Turnkey workflows can help you prototype your Simulink/MATLAB algorithm on FPGA/SoC boards.

IP Core Generation workflow adopts the IP-centric design methodology. You can generate your own custom HDL IP core from your Simulink/MATLAB algorithm. This custom IP core is sharable and reusable, and also comes with a generated IP core report.

http://www.mathworks.com/help/releases/R2015a/hdlcoder/ug/custom-ip-core-generation.html

http://www.mathworks.com/discovery/ip-core-generation.html?s_tid=srchtitle

You can then integrate the generated IP core into a larger design in FPGA design tools such as Altera Qsys, or Xilinx Vivado/IP Integrator. You can also register your Vivado/Qsys project as a custom reference design, so the IP Core Generation workflow can help you integrate the IP core into the reference design automatically.

http://www.mathworks.com/help/releases/R2015a/hdlcoder/examples/define-and-register-custom-board-and-reference-design-for-soc-workflow.html

FPGA Turnkey workflow does not use the IP-centric design methodology. Instead, it generates the HDL codes for the whole FPGA design, including the algorithm HDL code, the FPGA top level wrapper HDL code, and FPGA Pin mapping constraints, so you can run your algorithm on standard alone FPGA board. FPGA Turnkey workflow targets FPGA boards only, it does not support Zynq/Altera SoC boards

http://www.mathworks.com/help/releases/R2015a/hdlcoder/xilinx-fpga-boards.html

Thanks, Wang

MATLAB: Altera FPGAs

Hi Natalie,

Yes, you need a separate Altera FPGA board to prototype Altera Arria II Gx FPGA.

Altera FPGA boards are supported starting in R2012a release. HDL Coder and HDL Verifier support the following Altera development boards. You can use the first one in the list to prototype Arria FPGA.

    Altera Arria II GX FPGA development kit
    Altera Cyclone III FPGA development kit
    Altera Cyclone IV GX FPGA development kit
    Altera DE2-115 development and education board

Link to the document: http://www.mathworks.com/help/toolbox/hdlcoder/rn/bqmfe_z-10.html#btbo0bg-1

Thanks, Wang

Best Answer

Related Solutions

MATLAB: What is the difference between FPGA Turnkey and IP Core Generation

MATLAB: Altera FPGAs

Related Question