MATLAB: HDL Code Generation of a system that includes Model References results in the generated code for the referenced model having its name (entity) duplicated.

Question

If I have a referenced model (e.g. adder) within a design (e.g. DUT); when I generate the code for DUT it contains the expected component instantion in DUT VHDL e.g. u_adder : adder however the generated VHDLfor the adder component is incorrectly named adder_adder.vhd with an enity name adder_adder therefore there is a mismatch in simulation/synthesis.

If you generate the code for adder standalone it will generate the correct filename adder.vhd with enitty name adder.

Please explain how you can generate VHDL code for designs that contain referenced models.

Answer 1

Hi James,

HDL Coder adds a prefix for the referenced model in the generated code. The default value of that prefix is the modelname_, where ‘modelname’ is the name of the referenced model. This is the reason for the adder_adder.vhd in your design.

You can always control the prefix using the HDL Block Property - ReferenceModelPrefix. (Right click on the referenced model > HDL Code > HDL Block Properties). If you provide an empty prefix, HDL Coder will not add a prefix to the submodel file name and you will get ‘adder.vhd’ with entity name ‘adder’. But if there are any name collisions between the different models that you use, this can result in compilation errors.

regards,

Sreejith