MATLAB: Do I get a rate transition error about asynchronously executed block

I received the following error when I run a Speedgoat example:
IO3xx_coprocessor_hdlc_slrt.slx
ERROR: Because the block 'IO3xx_coprocessor_hdlc_slrt/DMA_Engine/IRQ_CPU_Calc_Disabled/DMA from FPGA/DMA read' is asynchronously executed, destination at output port 1 must be a rate transition, or root output port that inherits sample time, or an asynchronous function-call subsystem. 
Component:Simulink | Category:Block diagram error

Best Answer

The reason you received the error is because the block 'IO3xx_coprocessor_hdlc_slrt/DMA_Engine/IRQ_CPU_Calc_Disabled/DMA from FPGA/DMA read' is asynchronously executed. To resolve the error, consider adding a "Rate Transition" block in between the DMA read block and the output port.
For more information about this block, refer to the following page:
https://www.mathworks.com/help/simulink/slref/ratetransition.html
To learn more about asynchronous event, refer to this example:
https://www.mathworks.com/help/releases/R2020a/xpc/ug/asynchronous-transition.html
 
Related Question