MATLAB: Generate C code for FPGA

simulink

Hello,

Is it possible to generate C code for FPGA ? ( Atmel Arria V ) I only familiar with generaing c code for ARM, and generating HDL code for FPGA, but not "generate C code for FPGA". Is it possible ? Is there any tutorial on this subject ?

Thank you, Ran

Best Answer

Hi Ran,

The recommended workflow is to use HDL Coder to generate HDL Code and IP core for Altera SoC FPGA fabric, and use Embedded Coder to generate C code to program the ARM processor on the same chip. Please see following pages for examples and videos:

Thanks, Wang

Related Solutions

MATLAB: Altera FPGAs

Hi Natalie,

Yes, you need a separate Altera FPGA board to prototype Altera Arria II Gx FPGA.

Altera FPGA boards are supported starting in R2012a release. HDL Coder and HDL Verifier support the following Altera development boards. You can use the first one in the list to prototype Arria FPGA.

    Altera Arria II GX FPGA development kit
    Altera Cyclone III FPGA development kit
    Altera Cyclone IV GX FPGA development kit
    Altera DE2-115 development and education board

Link to the document: http://www.mathworks.com/help/toolbox/hdlcoder/rn/bqmfe_z-10.html#btbo0bg-1

Thanks, Wang

MATLAB: What is the difference between FPGA Turnkey and IP Core Generation

Hi Yashar,

Both IP Core Generation and FPGA Turnkey workflows can help you prototype your Simulink/MATLAB algorithm on FPGA/SoC boards.

IP Core Generation workflow adopts the IP-centric design methodology. You can generate your own custom HDL IP core from your Simulink/MATLAB algorithm. This custom IP core is sharable and reusable, and also comes with a generated IP core report.

http://www.mathworks.com/help/releases/R2015a/hdlcoder/ug/custom-ip-core-generation.html

http://www.mathworks.com/discovery/ip-core-generation.html?s_tid=srchtitle

You can then integrate the generated IP core into a larger design in FPGA design tools such as Altera Qsys, or Xilinx Vivado/IP Integrator. You can also register your Vivado/Qsys project as a custom reference design, so the IP Core Generation workflow can help you integrate the IP core into the reference design automatically.

http://www.mathworks.com/help/releases/R2015a/hdlcoder/examples/define-and-register-custom-board-and-reference-design-for-soc-workflow.html

FPGA Turnkey workflow does not use the IP-centric design methodology. Instead, it generates the HDL codes for the whole FPGA design, including the algorithm HDL code, the FPGA top level wrapper HDL code, and FPGA Pin mapping constraints, so you can run your algorithm on standard alone FPGA board. FPGA Turnkey workflow targets FPGA boards only, it does not support Zynq/Altera SoC boards

http://www.mathworks.com/help/releases/R2015a/hdlcoder/xilinx-fpga-boards.html

Thanks, Wang

Best Answer

Related Solutions

MATLAB: Altera FPGAs

MATLAB: What is the difference between FPGA Turnkey and IP Core Generation

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