MATLAB: For HDL code generation, the float point to fixed point conversion is ok. Because of “Accounting for output port latency: 10 cycles”, the test bench does not agree with the HDL code. How to solve this problem

Question

For HDL code generation, the float point to fixed point conversion is ok. Because of "Accounting for output port latency: 10 cycles", the test bench does not agree with the HDL code. How to solve this problem?

Answer 1

The HDL testbench will account for this latency. So generating the HDL code and testbench will let you run the modified testbench with the appropriate latency of 10 cycles.

If you want to balance the delay added in one path to the other, turn Balance Delays option on and the parallel paths will get an additional latency of 10 cycles to match.