Dear My friends!
Now i have some problems in HDL simulink coder that need your helping. When i convert my code from simulink to verilog and after that i cosimulate it with modelsim, I have got an error between two results.
http://i1297.photobucket.com/albums/ag25/Dung_Pham_Van/error_zps3efd15af.gif
Anyone have any experimental to solve this problem?? please give me some suggestions.
Thanks with best regard!
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