MATLAB: Does Simulink Design Verifier dead logic analysis depend on model inputs
deaddetectinputslogicmodelSimulink Design Verifier
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Decision Coverage in Simulink is defined as:
"Decision coverage analyzes elements that represent decision points in a model, such as a Switch block or Stateflow® states. For each item, decision coverage determines the percentage of the total number of simulation paths through the item that the simulation traversed."
Since the AND output is not driving a decision making block, there is no decision coverage to collect. By adding a switch that is being driven by the AND block, you can observe that the decision coverage is reported:
The AND block will need to have Condition coverage enabled to examine the level of coverage it has. Condition coverage verifies that all combinations of inputs are tested for a given Logical operator block.
It is possible to do so by first saving your filter to a file, and then setting the filter (CovFilter) in the model.
Please refer to the following steps:
1. Open Simulink model:
>> slvnvdemo_covfilt
2. Right click on 'Normal config (feedthrough)' > Coverage > Exclude subsystem with all descendants
3. For Rationale, type 'myRationale', then Apply
4. From the Filter Viewer, click on Save Filter and save as 'myFilter.cvf'
5. In Configuration Parameters, navigate to Coverage > Advanced Parameters > Coverage filter filename, and specify name of the filer ('myFilter' in this case)
This can also be done programmatically as follows:
>> set_param(gcs,'CovFilter','myFilter')
6. From the model, click on Analysis > Test manager
7. New > Test File, and save as 'myTest.mldatx'
8. For System under test, select 'use current model'
9. In the Test File 'myTest', navigate to Coverage settings and select 'Record coverage for system under test'
10. Run test
Now, go to the Results and Artifacts section, navigate to Aggregated Coverage Results to generate report, and verify that SubSystem block "Normal config (feedthrough)" has been excluded from coverage analysis.
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