MATLAB: Does Real-Time Workshop 6.3 (R14SP3) generate non optimal code for automatically inserted Rate Transition blocks

realsimulink codertime

I have a model in which I have selected "Automatically handle data transfers between tasks" in the Configurations Parameters dialog. The generated code for the model includes several IF statements that correspond to automatically inserted Rate Transition blocks. Each of the IF statements tests the same condition. The code could be optimized by combining the several IF statements into a single IF statement. The following section of code illustrates the issue:

 /* RateTransition: '<S14>/TmpRTBAtBusCtrlInport1' incorporates:
    *  Inport: '<Root>/AnyAxisEnabledInput'
    */
   if(KinetixMbc_M->Timing.RateInteraction.TID0_1) {
     KinetixMbc_B.TmpRTBAtBusCtrlInport1 = CtrlFlags.AnyAxisEnabledInput;
   }
   /* Gain: '<S14>/FLT1Convert' incorporates:
    *  Inport: '<Root>/FLT1_HW'
    */
   rtb_FLT1 = KCL->FLT1_HW;
   /* RateTransition: '<S14>/TmpRTBAtBusCtrlInport7' */
   if(KinetixMbc_M->Timing.RateInteraction.TID0_1) {
     KinetixMbc_B.TmpRTBAtBusCtrlInport7 = rtb_FLT1;
   }
   /* Gain: '<S14>/VbusConvert' incorporates:
    *  DataTypeConversion: '<S14>/VbusCast'
    *  Inport: '<Root>/Vbus_HW'
    */
   Ireg.Vbus = (real_T)KCL->Vbus_HW * Pwr.VbusBitsToVolts;
   /* RateTransition: '<S14>/TmpRTBAtBusCtrlInport8' */
   if(KinetixMbc_M->Timing.RateInteraction.TID0_1) {
     KinetixMbc_B.TmpRTBAtBusCtrlInport8 = Ireg.Vbus;
   }
   /* RateTransition: '<S14>/Rate Transition' incorporates:
    *  Inport: '<Root>/ExcptResetInput'
    */
   if(KinetixMbc_M->Timing.RateInteraction.TID0_1) {
     KinetixMbc_B.Reset_a = CtrlFlags.ExcptResetInput;
   }

Best Answer

Real-Time Workshop 6.3 (R14SP3) generates an IF statement whenever it sees a Rate Transition block in the model. It does not optimize the code by combining all IF statements that check for the same condition.

There are no workarounds.

Related Solutions

MATLAB: Do I get redundant if conditions when I use a multirate system with SingleTasking mode

If you would like to have just one if statement in the generated code you can group the blocks with the same sample rates in one subsystem and set the subsystem to an atomic unit and set the option

"Real-Time Workshop system code" set to "Inline" then you will receive the following code:

    54     if (GroupCode_v2_M->Timing.TaskCounters.TID[1] == 0) {
     55       /* Outputs for atomic SubSystem: '<Root>/Subsystem' */
     56   
     57       /* Gain: '<S1>/TsB' incorporates:
     58        *  Inport: '<Root>/in1'
     59        */
     60       GroupCode_v2_B.TsB = GroupCode_v2_P.TsB_Gain * GroupCode_v2_U.in1;
     61   
     62       /* Gain: '<S1>/TsB1' incorporates:
     63        *  Inport: '<Root>/in1'
     64        */
     65       GroupCode_v2_B.TsB1 = GroupCode_v2_P.TsB1_Gain * GroupCode_v2_U.in1;
     66   
     67       /* Gain: '<S1>/TsB2' incorporates:
     68        *  Inport: '<Root>/in1'
     69        */
     70       GroupCode_v2_B.TsB2 = GroupCode_v2_P.TsB2_Gain * GroupCode_v2_U.in1;
     71   
     72       /* end of Outputs for SubSystem: '<Root>/Subsystem' */
     73     }

MATLAB: What is the difference between ImplicitReceive and ExplicitReceive in AUTOSAR Code

In the AUTOSAR sense for the RTE, the main difference is the following:

ImplicitReceive: The input is always buffered. So, the input value remains the same in a single execution of the runnable, no matter how many times it is used.
ExplicitReceive: The input is not buffered. So, the input value changes whenever it is used within a single execution of the runnable.

However, when generating code from Simulink, the code for the explicit case can be seen as buffered in the code, as shown in the examples below:

1) ImplicitReceive

/* Model step function for TID1 */
void Runnable_2s(void)                 /* Sample time: [2.0s, 0.0s] */
{
  /* Update for RateTransition: '<Root>/RateTransition' incorporates:
   *  DiscreteIntegrator: '<Root>/Integrator'
   */
  Rte_IrvIWrite_Runnable_2s_IRV1(rtDW.Integrator_DSTATE);
    /* Update for DiscreteIntegrator: '<Root>/Integrator' incorporates:
     *  Inport: '<Root>/In2_2s'
     */
    rtDW.Integrator_DSTATE += 2.0 * Rte_IRead_Runnable_2s_ReceivePort_In2();
  }

2) ExplicitReceive

/* Model step function for TID1 */
void Runnable_2s(void)                 /* Sample time: [2.0s, 0.0s] */
{
  real_T tmpRead;
    /* Inport: '<Root>/In2_2s' */
    Rte_Read_ReceivePort_In2(&tmpRead);
    /* Update for RateTransition: '<Root>/RateTransition' incorporates:
     *  DiscreteIntegrator: '<Root>/Integrator'
     */
    Rte_IrvIWrite_Runnable_2s_IRV1(rtDW.Integrator_DSTATE);
    /* Update for DiscreteIntegrator: '<Root>/Integrator' */
    rtDW.Integrator_DSTATE += 2.0 * tmpRead;
  }

As it can be observed from the code above, the explicit case can be considered buffered in the sense that "tmpRead" is used in the algorithm instead of direct calls to "Rte_Read".

This is required in order to make code and simulation behaviors match, because in Simulink there is no notion of a signal line changing value in the middle of a time step between downstream blocks reading it, for example.

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