I am currently trying to use the FPGA-in-the-loop Wizard for the Microsemi Polarfire Evalboard, but I'm unable to continue with the example as I get the following error on MATLAB R2019a, using Libero SoC v11.8 IDE:
### HDL compilation failed.### Libero SoC returned the following error message:Error: Parameter 'instantiate_in_smartdesign' is not defined. Valid command formatting is 'new_project -location "project location" -name "project name" [-project_description "project description"] [-block_mode "TRUE | FALSE"] [-standalone_peripheral_initialization "TRUE | FALSE"] [-use_enhanced_constraint_flow "TRUE | FALSE"] -hdl "VHDL | VERILOG" -family "family" [-die "die"] [-package "package"] [-speed "speed"] [-die_voltage "die_voltage"] [-part_range "part_range"] [-adv_options "adv_options"]* 'Error: Failure when executing Tcl script. [ Line 58: Error in command new_project ]Error: The Execute Script command failed
Using Libero SoC v11.8 SP3, the error is slightly different and mentions a different unknown parameter:
### HDL compilation failed.### Libero SoC returned the following error message:Error: Parameter 'ondemand_build_dh' is not defined....
Best Answer