MATLAB: Dear Sir, I have written LU Decomposition code for 8X8 matrix in MATLAB and converted into VHDL using HDL coder but when I am synthesizing it it is demanding more FPGA pins that the FPGA has, even the FPGA is having more than 600 pins.

HDL Coder

When I did LU Decomposition in MATLAB, my L and U matrices have -ve as well as floating point numbers. I have converted the MATLAB code into VHDL using HDL Coder while choosing the option "convert to fix point at build time" . When I am synthesizing it is asking more FPGA pins and not getting synthesized. Please suggest how can I make my code synthesized? I am attaching code:
LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.ALL; USE work.LUDecomposition_fixpt_pkg.ALL;
ENTITY LUDecomposition_fixpt IS PORT( a11 : IN std_logic_vector(2 DOWNTO 0); — ufix3 a12 : IN std_logic_vector(3 DOWNTO 0); — ufix4 a13 : IN std_logic_vector(3 DOWNTO 0); — ufix4 a14 : IN std_logic_vector(2 DOWNTO 0); — ufix3 a15 : IN std_logic_vector(3 DOWNTO 0); — ufix4 a16 : IN std_logic_vector(3 DOWNTO 0); — ufix4 a17 : IN std_logic_vector(2 DOWNTO 0); — ufix3 a18 : IN std_logic_vector(3 DOWNTO 0); — ufix4 a21 : IN std_logic_vector(2 DOWNTO 0); — ufix3 a22 : IN std_logic_vector(4 DOWNTO 0); — ufix5 a23 : IN std_logic_vector(4 DOWNTO 0); — ufix5 a24 : IN std_logic_vector(5 DOWNTO 0); — ufix6 a25 : IN std_logic_vector(3 DOWNTO 0); — ufix4 a26 : IN std_logic_vector(7 DOWNTO 0); — ufix8 a27 : IN std_logic_vector(5 DOWNTO 0); — ufix6 a28 : IN std_logic_vector(3 DOWNTO 0); — ufix4 a31 : IN std_logic_vector(5 DOWNTO 0); — ufix6 a32 : IN std_logic_vector(3 DOWNTO 0); — ufix4 a33 : IN std_logic_vector(3 DOWNTO 0); — ufix4 a34 : IN std_logic_vector(5 DOWNTO 0); — ufix6 a35 : IN std_logic_vector(5 DOWNTO 0); — ufix6 a36 : IN std_logic_vector(3 DOWNTO 0); — ufix4 a37 : IN std_logic_vector(5 DOWNTO 0); — ufix6 a38 : IN std_logic_vector(3 DOWNTO 0); — ufix4 a41 : IN std_logic_vector(5 DOWNTO 0); — ufix6 a42 : IN std_logic_vector(5 DOWNTO 0); — ufix6 a43 : IN std_logic_vector(5 DOWNTO 0); — ufix6 a44 : IN std_logic_vector(6 DOWNTO 0); — ufix7 a45 : IN std_logic_vector(6 DOWNTO 0); — ufix7 a46 : IN std_logic_vector(5 DOWNTO 0); — ufix6 a47 : IN std_logic_vector(5 DOWNTO 0); — ufix6 a48 : IN std_logic_vector(5 DOWNTO 0); — ufix6 a51 : IN std_logic_vector(4 DOWNTO 0); — ufix5 a52 : IN std_logic_vector(5 DOWNTO 0); — ufix6 a53 : IN std_logic_vector(5 DOWNTO 0); — ufix6 a54 : IN std_logic_vector(4 DOWNTO 0); — ufix5 a55 : IN std_logic_vector(7 DOWNTO 0); — ufix8 a56 : IN std_logic_vector(5 DOWNTO 0); — ufix6 a57 : IN std_logic_vector(4 DOWNTO 0); — ufix5 a58 : IN std_logic_vector(5 DOWNTO 0); — ufix6 a61 : IN std_logic_vector(4 DOWNTO 0); — ufix5 a62 : IN std_logic_vector(4 DOWNTO 0); — ufix5 a63 : IN std_logic_vector(5 DOWNTO 0); — ufix6 a64 : IN std_logic_vector(5 DOWNTO 0); — ufix6 a65 : IN std_logic_vector(4 DOWNTO 0); — ufix5 a66 : IN std_logic_vector(3 DOWNTO 0); — ufix4 a67 : IN std_logic_vector(5 DOWNTO 0); — ufix6 a68 : IN std_logic_vector(5 DOWNTO 0); — ufix6 a71 : IN std_logic_vector(3 DOWNTO 0); — ufix4 a72 : IN std_logic_vector(4 DOWNTO 0); — ufix5 a73 : IN std_logic_vector(4 DOWNTO 0); — ufix5 a74 : IN std_logic_vector(2 DOWNTO 0); — ufix3 a75 : IN std_logic_vector(5 DOWNTO 0); — ufix6 a76 : IN std_logic_vector(5 DOWNTO 0); — ufix6 a77 : IN std_logic_vector(4 DOWNTO 0); — ufix5 a78 : IN std_logic_vector(5 DOWNTO 0); — ufix6 a81 : IN std_logic_vector(5 DOWNTO 0); — ufix6 a82 : IN std_logic_vector(2 DOWNTO 0); — ufix3 a83 : IN std_logic_vector(6 DOWNTO 0); — ufix7 a84 : IN std_logic_vector(5 DOWNTO 0); — ufix6 a85 : IN std_logic_vector(5 DOWNTO 0); — ufix6 a86 : IN std_logic_vector(5 DOWNTO 0); — ufix6 a87 : IN std_logic_vector(5 DOWNTO 0); — ufix6 a88 : IN std_logic_vector(6 DOWNTO 0); — ufix7 LU1 : OUT std_logic_vector(17 DOWNTO 0); — ufix18_En10 LM : OUT vector_of_signed24(0 TO 63); — ufix4 UM : OUT vector_of_signed24(0 TO 63); clock : in std_logic ); END LUDecomposition_fixpt;
ARCHITECTURE rtl OF LUDecomposition_fixpt IS
-- Constants
CONSTANT nc : vector_of_signed24(0 TO 63) := (to_signed(16#000400#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000400#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000400#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000400#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000400#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000400#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000400#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000000#, 24),
to_signed(16#000400#, 24)); -- sfix24 [64]
CONSTANT C_divbyzero_p : signed(47 DOWNTO 0) := signed'(X"7FFFFFFFFFFF"); -- sfix48
CONSTANT C_divbyzero_n : signed(47 DOWNTO 0) := signed'(X"800000000000"); -- sfix48
CONSTANT c_divbyzero_p_0 : signed(42 DOWNTO 0) := signed'("0111111111111111111111111111111111111111111"); -- sfix43
CONSTANT c_divbyzero_n_0 : signed(42 DOWNTO 0) := signed'("1000000000000000000000000000000000000000000"); -- sfix43
-- Signals
SIGNAL a11_unsigned : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL a12_unsigned : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL a13_unsigned : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL a14_unsigned : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL a15_unsigned : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL a16_unsigned : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL a17_unsigned : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL a18_unsigned : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL a21_unsigned : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL a22_unsigned : unsigned(4 DOWNTO 0); -- ufix5
SIGNAL a23_unsigned : unsigned(4 DOWNTO 0); -- ufix5
SIGNAL a24_unsigned : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL a25_unsigned : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL a26_unsigned : unsigned(7 DOWNTO 0); -- ufix8
SIGNAL a27_unsigned : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL a28_unsigned : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL a31_unsigned : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL a32_unsigned : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL a33_unsigned : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL a34_unsigned : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL a35_unsigned : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL a36_unsigned : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL a37_unsigned : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL a38_unsigned : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL a41_unsigned : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL a42_unsigned : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL a43_unsigned : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL a44_unsigned : unsigned(6 DOWNTO 0); -- ufix7
SIGNAL a45_unsigned : unsigned(6 DOWNTO 0); -- ufix7
SIGNAL a46_unsigned : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL a47_unsigned : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL a48_unsigned : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL a51_unsigned : unsigned(4 DOWNTO 0); -- ufix5
SIGNAL a52_unsigned : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL a53_unsigned : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL a54_unsigned : unsigned(4 DOWNTO 0); -- ufix5
SIGNAL a55_unsigned : unsigned(7 DOWNTO 0); -- ufix8
SIGNAL a56_unsigned : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL a57_unsigned : unsigned(4 DOWNTO 0); -- ufix5
SIGNAL a58_unsigned : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL a61_unsigned : unsigned(4 DOWNTO 0); -- ufix5
SIGNAL a62_unsigned : unsigned(4 DOWNTO 0); -- ufix5
SIGNAL a63_unsigned : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL a64_unsigned : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL a65_unsigned : unsigned(4 DOWNTO 0); -- ufix5
SIGNAL a66_unsigned : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL a67_unsigned : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL a68_unsigned : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL a71_unsigned : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL a72_unsigned : unsigned(4 DOWNTO 0); -- ufix5
SIGNAL a73_unsigned : unsigned(4 DOWNTO 0); -- ufix5
SIGNAL a74_unsigned : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL a75_unsigned : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL a76_unsigned : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL a77_unsigned : unsigned(4 DOWNTO 0); -- ufix5
SIGNAL a78_unsigned : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL a81_unsigned : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL a82_unsigned : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL a83_unsigned : unsigned(6 DOWNTO 0); -- ufix7
SIGNAL a84_unsigned : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL a85_unsigned : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL a86_unsigned : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL a87_unsigned : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL a88_unsigned : unsigned(6 DOWNTO 0); -- ufix7
SIGNAL LU1_tmp : unsigned(17 DOWNTO 0); -- ufix18_En10
BEGIN a11_unsigned <= unsigned(a11);

a12_unsigned <= unsigned(a12);
a13_unsigned <= unsigned(a13);
a14_unsigned <= unsigned(a14);
a15_unsigned <= unsigned(a15);
a16_unsigned <= unsigned(a16);
a17_unsigned <= unsigned(a17);
a18_unsigned <= unsigned(a18);
a21_unsigned <= unsigned(a21);
a22_unsigned <= unsigned(a22);
a23_unsigned <= unsigned(a23);
a24_unsigned <= unsigned(a24);
a25_unsigned <= unsigned(a25);
a26_unsigned <= unsigned(a26);
a27_unsigned <= unsigned(a27);
a28_unsigned <= unsigned(a28);
a31_unsigned <= unsigned(a31);
a32_unsigned <= unsigned(a32);
a33_unsigned <= unsigned(a33);
a34_unsigned <= unsigned(a34);
a35_unsigned <= unsigned(a35);
a36_unsigned <= unsigned(a36);
a37_unsigned <= unsigned(a37);
a38_unsigned <= unsigned(a38);
a41_unsigned <= unsigned(a41);
a42_unsigned <= unsigned(a42);
a43_unsigned <= unsigned(a43);
a44_unsigned <= unsigned(a44);
a45_unsigned <= unsigned(a45);
a46_unsigned <= unsigned(a46);
a47_unsigned <= unsigned(a47);
a48_unsigned <= unsigned(a48);
a51_unsigned <= unsigned(a51);
a52_unsigned <= unsigned(a52);
a53_unsigned <= unsigned(a53);
a54_unsigned <= unsigned(a54);
a55_unsigned <= unsigned(a55);
a56_unsigned <= unsigned(a56);
a57_unsigned <= unsigned(a57);
a58_unsigned <= unsigned(a58);
a61_unsigned <= unsigned(a61);
a62_unsigned <= unsigned(a62);
a63_unsigned <= unsigned(a63);

Best Answer

It appears that your MATLAB code has 64 separate inputs, and that fixpt conversion is selecting anywhere from 3 to 7 bits per input. if I guess a median value of 5 bits per pin, this accounts for 320 pins. You will need to stream these inputs in one at a time, most likely, either using them in a streaming fashion or storing them in a RAM, as your algorithm requires.
In addition, you are generating two output vectors that are 24 * 64 bits, which is 1536 pins for each of these two outputs. Once again, you need to serialize the outputs and stream the data out rather than requesting such large arrays. Worst case you can use a RAM to buffer the outputs and start streaming them out once enough data has been calculated.
I don't know the internals of your algorithm, but you do. You may need no buffering, line/column buffers, or full IO matrix buffering; it depends on your algorithm and implementation. In any case you should be able to drop the input pin requirement to that needed for a single input element. The two outputs should likewise be able to be reduced to a pair of 64-bit streaming outputs. If pins are really restricted you should be able to multiplex the output, and reduce the 128 bits to 64.