I'm using "FPGA in the loop" with xilinx zc706 board. The only supported communication way is jtag. if I want run my code faster,should I buy a new board with eth support or pcie support? As we all know ,JTAG is slow ,ETH and PCIe is faster. Does MathWork's "FPGA in the loop" framework support to full the phy interface speed?
MATLAB: Communication Speed of “FPGA in the loop” in different communication ways
fpga in the loopHDL CoderHDL VerifierMATLAB
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