Hello, I'm now using HDL coder to generate VHDL code from my model named simple_timer_model. And then program it to the target device(Xilinx Zedboard). I encontered some errors and warnings in the stage 2.3 check Block Comatibility of HDL workflow adviser. Here is the list of the Warnings:
DL Code Generation Check Report for simple_timer_model/CPU Timer 0 Generated on 2014-02-21 10:37:05 The following table describes blocks for which errors, warnings or messages were reported.
Simulink Block Level Description simple_timer_model/CPU Timer 0/Triggered Subsystem1/Trigger Error'Output port 'Out1' must have an initial value of 0 for HDL code generation.
simple_timer_model/CPU Timer 0/Triggered Subsystem2/Trigger Error'Output port 'Out1' must have an initial value of 0 for HDL code generation.
simple_timer_model/CPU Timer 0/Triggered Subsystem4/Trigger Error'Output port 'Out1' must have an initial value of 0 for HDL code generation.
simple_timer_model/CPU Timer 0/CPU-Timer 0, Control Register Read WarningCannot find the implementation for block 'simple_timer_model/CPU Timer 0/CPU-Timer 0, Control Register Read'.
simple_timer_model/CPU Timer 0/CPU-Timer 0, Control Register Read TRB(5:5) WarningCannot find the implementation for block 'simple_timer_model/CPU Timer 0/CPU-Timer 0, Control Register Read TRB(5:5)'.
simple_timer_model/CPU Timer 0/CPU-Timer 0, Control Register Read1 WarningCannot find the implementation for block 'simple_timer_model/CPU Timer 0/CPU-Timer 0, Control Register Read1'.
simple_timer_model/CPU Timer 0/CPU-Timer 0, Control Register Write1 WarningCannot find the implementation for block 'simple_timer_model/CPU Timer 0/CPU-Timer 0, Control Register Write1'.
simple_timer_model/CPU Timer 0/CPU-Timer 0, Period Register Read WarningCannot find the implementation for block 'simple_timer_model/CPU Timer 0/CPU-Timer 0, Period Register Read'.
simple_timer_model/CPU Timer 0/CPU-Timer 0, Prescale Register Read WarningCannot find the implementation for block 'simple_timer_model/CPU Timer 0/CPU-Timer 0, Prescale Register Read'.
simple_timer_model/CPU Timer 0/CPU-Timer 0, Prescale Register Read1 WarningCannot find the implementation for block 'simple_timer_model/CPU Timer 0/CPU-Timer 0, Prescale Register Read1'.
simple_timer_model/CPU Timer 0/Data Store Read WarningCannot find the implementation for block 'simple_timer_model/CPU Timer 0/Data Store Read'.
simple_timer_model/CPU Timer 0/Data Store Write WarningCannot find the implementation for block 'simple_timer_model/CPU Timer 0/Data Store Write'.
simple_timer_model/CPU Timer 0/Data Store Write1 WarningCannot find the implementation for block 'simple_timer_model/CPU Timer 0/Data Store Write1'.
simple_timer_model/CPU Timer 0/TIMER0PRD WarningCannot find the implementation for block 'simple_timer_model/CPU Timer 0/TIMER0PRD'.
simple_timer_model/CPU Timer 0/TIMER0TCR WarningCannot find the implementation for block 'simple_timer_model/CPU Timer 0/TIMER0TCR'.
simple_timer_model/CPU Timer 0/TIMER0TIM WarningCannot find the implementation for block 'simple_timer_model/CPU Timer 0/TIMER0TIM'.
simple_timer_model/CPU Timer 0/TIMER0TPR WarningCannot find the implementation for block 'simple_timer_model/CPU Timer 0/TIMER0TPR'.
simple_timer_model/CPU Timer 0/Triggered Subsystem/IC1 WarningCannot find the implementation for block 'simple_timer_model/CPU Timer 0/Triggered Subsystem/IC1'.
simple_timer_model/CPU Timer 0/Triggered Subsystem1/IC WarningCannot find the implementation for block 'simple_timer_model/CPU Timer 0/Triggered Subsystem1/IC'.
simple_timer_model/CPU Timer 0/Triggered Subsystem2/IC WarningCannot find the implementation for block 'simple_timer_model/CPU Timer 0/Triggered Subsystem2/IC'.
I use the block memory the simulate the behavior of 4 registers in the Timer module, and in the Triggerd subsystem block( with which I use to triger the signal transaction with a unity delay by pulse signal), I have configured the parameter 'InitialOutput' of block 'Out1' to [0], and the error still exist.
Please help me to debug my system design.
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