I am trying to convert my HDL coder project to verilog files via HDL coder workflow.
This error HDL code generation report.
Error Assertion failed: b:\matlab\src\cgir_hdl\pir_transforms\datarateanalyzer.cpp:582:PirUtils::floatEqual(data.getRate(), outputSig->getRate())Failed Assertion failed: b:\matlab\src\cgir_hdl\pir_transforms\datarateanalyzer.cpp:582:PirUtils::floatEqual(data.getRate(), outputSig->getRate()) Assertion failed:b:\matlab\src\cgir_hdl\pir_transforms\datarateanalyzer.cpp:582:PirUtils::floatEqual(data.getRate(), outputSig->getRate())Error in slhdlcoder.HDLCoder/makehdlError in downstream.DownstreamIntegrationDriver/runGenerateRTLCodeAndTestbenchError in runGenerateRTLCodeAndTestbenchError in Simulink.ModelAdvisor/executeCheckCallbackFctError in Simulink.ModelAdvisor/runError in Simulink.ModelAdvisor/runCheckError in ModelAdvisor.Node/runTaskAdvisorError in ModelAdvisor.Node/runToFailError in ModelAdvisor.Node.runtofailureFailed Generated HDL code.
Please suggest me how to proceed. I am using Matlab 2017a.
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