It is unclear to me why Simulink flagged this as an algebraic loop:
Assuming the delay block is effectively nothing more than a D-flip flop, and also assuming that the enable input of the delay block is synchronous (sensitive to the clock edge driving the delay block), then the delayed output is a reflection of the state of the inputs (including the enable) one time step later and NOT the same instance in time as the inputs. The delay block has a defined initial condition of 0, so the initial condition of the enable is also known. I cannot figure out why Simulink thinks this is an algebraic loop.
Adding an additional delay between the delayed output and the enable would break the design.
Thoughts? Is there a difference between this delay block and a D-flip flop?
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