MATLAB: About HDL simulink coder

Question

Dear friends, I have an error when I try to convert StateFlow Block to Verilog: * Failed network:propagateClockRate:ratesDontMatch: When propagating rates on , signal *

Anybody can help me!

Thanks you so much!

Pham Van Dung

Answer 1

Hi Pham,

Can you send me the model that reproduce the failure? thanks.

kiran.kintali@mathworks.com