[Math] In what instance would a four bit parallel adder’s initial carry-in be 1

binarybinary operationslogic

In class we are creating multiple bit adders. One full adder for each bit being added with the following adder taking the previous one's "Carry-in" value as input. I understand the logic behind this, however what I was wondering is in what instance would the initial Carry-in value (C₀ in this picture) would be 1?

If you are adding the first two bits, wouldn't the initial carry-in always be zero considering that nothing has been added yet? Couldn't the first full adder be substituted with a half adder and still work?

Best Answer

The initial carry-in in your picture is $C_I,$ not $C_O,$ and it's tied to ground so that it's always $0.$ So yes, the first full adder (Adder 1) could be replaced by a half-adder.

However, there are some reasons that you might want to keep the full adder and make that input $C_I$ actually available for use, rather than having it permanently tied to ground:

$\bullet$ This is a 4-bit adder. Maybe you want to take two or more of these and hook them together to make an 8-bit adder (or a 16-bit adder or whatever). In that case the carry-out of each 4-bit adder would be connected to the carry-in of the next 4-bit adder.

$\bullet$ You might want to use this to implement subtraction. To subtract $A-B,$ where the numbers $A$ and $B$ are in two's-complement form, you'll complement all the bits of $B$ (by using four NOT gates in parallel) to get the four values $B',$ and you'll add $A+B'+1$ (because that's how two's-complement arithmetic works). The easiest way of doing this is to add $A$ and $B'$ with an adder like you have, but with the carry-in tied to $1$ instead of $0.$

$\bullet$ You could build a similar device that could either add or subtract, based on an extra selector input $Q$ which would be $0$ for addition and $1$ for subtraction. You would then use four XOR gates to XOR each of the 4 bits of $B$ with the selector input $Q$ to produce either the bits of $B$ (for addition) or the complement of the bits of $B$ (for subtraction). You would also connect $Q$ to the carry-in so that you would add an extra $1$ for subtraction but not for addition.

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