How does a defect rate scale with the area of a wafer

area

this is my first time posting here so hopefully I'm not breaking any rules. I have a fairly simple question but I can't seem to wrap my head around it. I'm currently reading "Computer architecture: A quantitative approach" and in chapter 1 the writers mention defect rates in integrated circuit wafers. A 28nm process will have "0.016-0.047 defects per square centimeter". I'm somehow not sure if this represents a percentage or simply a quantity, but I'm guessing it's not a percentage because percentages scale with any area, i.e. they wouldn't mention an area. I want to know how this would scale to square meters. I understand that cm^2 scales to m^2 by a factor of 10^4, so does this mean that the defects per square meters is 160-470? Or are there other factors to take into account when scaling areas like this?

Best Answer

Yes, that's correct.

'$0.016 - 0.047$ defects per square centimeter' means for $1$ square centimeter, there will be between $0.016$ and $0.047$ defects.

Therefore, for $1$ square meter $=$ $10^4$ square centimeters, there will be between $0.016 \cdot 10^4 = 160$ and $0.047 \cdot 10^4 = 470$ defects.